In transmitting serial digital data, it is necessary to provide a series of clock pulses in addition to the data in order to synchronize the coding of the transmitted serial data at the receiving terminal. In prior known transmitting schemes two channels were required for this purpose; one for date, and one for clock. In attempting to avoid the requirement for two such channels, and to eliminate certain difficulties in magnetic recording of serial digital data, self-clocking codes evolved as a result of combining clock and data signals. The Manchester code is one such self-clocking code. Manchester encoders accept clock and data and combine them into a single output which may then be transmitted via a single channel to the receiving terminal. When the self-clocking data arrives at the receiving terminal it is processed by the decoder which extracts separately both data and clock from the input self-clocking code.
The properties of Manchester code are well known in the art of digital communications and magnetic recording of digital data. Only the parameters related to an understanding of the present invention will be described. The Manchester code consists of a sequence of pulses whose widths can have either of two possible values, W or 2W, depending on the one, zero sequence of the data stream. The absolute values of W and 2W are dependent upon the rate of the data stream. For example, if the data rate is 2 MHz, W=250 ns and 2W=500 ns.
FIG. 1 shows a typical Manchester code decoder where D.sub.1 and D.sub.2 are equal fixed delays that are selected for a particular input data rate. The required delay value is one-third of the input data bit period. As a result of the signal passing through D.sub.1 and D.sub.2 three signals are created. These three signals are (1) the undelayed input signal to D.sub.1, (2) the signal delayed by D.sub.1 or one-third of a bit period, and (3) the signal delayed by D.sub.1 +D.sub.2 or two-thirds of a bit period. These three signals are then fed into the gates that follow the delays. The upper gate, an "AND" gate, is the "1"s detector. It decodes a "1" during any interval of "high" coincidence of these three input signals. The lower gate, a "NOR" gate, is the "0"s detector. It decodes a "0" when its three inputs are coincidentally "low." The outputs of the 1' s and 0's detectors are fed into a set-reset flip-flop composed of two input "NOR" gates. The output of this flip-flop provides the decoded Manchester data. Further logic combination of Manchester code and data provide the clock output.
Since delays D.sub.1 and D.sub.2 are fixed, the decoder is optimized for a single input data rate. Such a decoder cannot be used for input data rates which lie outside of this single frequency. In applications where a variety of data rates is expected, a separate decoder is required for each individual data rate.